View CAT524P-TE13_9092589.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ?2001 by catalyst semiconductor, inc. characteristics subject to change without notice features four 8-bit dpps configured as programmable voltage sources in dac-like applications common reference inputs buffered wiper outputs non-volatile nvram memory wiper storage output voltage range includes both supply rails 4 independently addressable buffered output wipers 1 lsb accuracy, high resolution serial p interface single supply operation: 2.7v-5.5v setting read-back without effecting outputs applications automated product calibration remote control adjustment of equipment offset, gain and zero adjustments in self-calibrating and adaptive control systems tamper-proof calibrations dac (with memory) substitute description the cat524 is a quad, 8-bit digitally-programmable potentiometer (dpp) configured for programmable voltage and dac-like applications. intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. the four independently programmable dpps have an output range which includes both supply rails. the wipers are buffered by rail to rail op amps. wiper settings, stored in non-volatile nvram memory, are not lost when the device is powered down and are automati- cally reinstated when power is returned. each wiper can be dithered to test new output values without effecting the stored settings, and stored settings can be read back without disturbing the dpp? output. the cat524 is controlled with a simple 3 wire serial interface. a chip select pin allows several devices to share a common serial interface. communication back to the host controller is via a single serial data line thanks to the tri-stated cat524 data output pin. a rdy/ bsy output working in concert with an internal low voltage detector signals proper operation of the non-volatile nvram memory erase/write cycle. the cat524 is available in the 0 to 70 c commercial and ?0 c to 85 c industrial operating temperature ranges. both 14-pin plastic dip and soic packages are offered. functional diagram pin configuration cat524 configured digitally programmable potentiometer (dpp): programmable voltage applications dip package (p) soic package (j) cat524 doc. no. 25076-00 4/01 m-1 rdy/ bsy clk cs prog di do v dd 2 3 4 13 12 11 5 6 7 10 9 8 114 gnd v ref h v out 1 v out 2 v out 3 v out 4 v ref l clk cs prog di do v dd 2 3 4 13 12 11 5 6 7 10 9 8 114 gnd v ref h v out 1 v out 2 v out 3 v out 4 v ref l cat 524 cat 524 rdy/ bsy rdy/bsy prog program control di cs clk serial control serial data output register gnd v l ref v h ref v dd 3114 7 5 2 4 v 1 13 11 10 6 12 out v 3 v 4 out v 2 out out do + + + + 9 8 nvram
cat524 2 doc. no. 25076-00 rev. 4/01 m-1 logic inputs i ih input leakage current v in = v dd 10 a i il input leakage current v in = 0v 10 a v ih high level input voltage 2 v dd v v il low level input voltage 0 0.8 v references v rh v ref h input voltage range 2.7 v dd v v rl v ref l input voltage range gnd v dd -2.7 v z in v ref h v ref l resistance 7 k ? logic outputs v oh high level output voltage i oh = 40 av dd 0.3 v v ol low level output voltage i ol = 1 ma, v dd = +5v 0.4 v i ol = 0.4 ma, v dd = +3v 0.4 v absolute maximum ratings* supply voltage v dd to gnd ...................................... 0.5v to +7v inputs clk to gnd ............................ 0.5v to v dd +0.5v cs to gnd .............................. 0.5v to v dd +0.5v di to gnd ............................... 0.5v to v dd +0.5v prog to gnd ........................ 0.5v to v dd +0.5v v ref h to gnd ........................ 0.5v to v dd +0.5v v ref l to gnd ......................... 0.5v to v dd +0.5v outputs d 0 to gnd ............................... 0.5v to v dd +0.5v v out 1 4 to gnd ................... 0.5v to v dd +0.5v operating ambient temperature commercial ( c or blank suffix) ...... 0 c to +70 c industrial ( i suffix) ...................... 40 c to +85 c junction temperature ..................................... +150 c storage temperature ....................... 65 c to +150 c lead soldering (10 sec max) .......................... +300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is not implied. device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. dc electrical characteristics: v dd = +2.7 to +5.5v, v ref h = v dd , v ref l = 0v, unless otherwise specified reliability characteristics symbol parameter min max units test method v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(2) latch-up 100 ma jedec standard 17 notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch-up protection is provided for stresses up to 100ma on address and data pins from 1v to v cc + 1v. symbol parameter conditions min typ max units resolution 8 bits accuracy inl integral linearity error i load = 10 a t r = c 1 lsb i load = 10 a t r = i 1 lsb i load = 40 a t r = c 2 lsb i load = 40 a t r = i 2 lsb dnl differential linearity error i load = 10 a t r = c 0.5 lsb i load = 10 a t r = i 0.5 lsb i load = 40 a t r = c 1.5 lsb i load = 40 a t r = i 1.5 lsb
cat524 3 doc. no. 25076-00 rev. 4/01 ac electrical characteristics: v dd = +2.7v to +5.5v, v ref h = +v dd , v ref l = 0v, unless otherwise specified symbol parameter conditions min typ max units digital t csmin minimum cs low time 150 ns t css cs setup time 100 ns t csh cs hold time 0 ns t dis di setup time 50 ns t dih di hold time 50 ns t do1 output delay to 1 150 ns t do0 output delay to 0 150 ns t hz output delay to high-z 400 ns t busy erase/write cycle time 45 ms t lz output delay to low-z 400 ns t prog erase/write pulse width 700 ns t ps prog setup time 150 ns t clk h minimum clk high time 500 ns t clk l minimum clk low time 300 ns f c clock frequency dc 1 mhz analog t ds dac settling time to 1/2 lsb c load = 10 pf, v dd = +5v 310 s c load = 10 pf, v dd = +3v 610 s pin capacitance c in input capacitance v in = 0v, f = 1 mhz (2) 8 pf c out output capacitance v out = 0v, f = 1 mhz (2) 6 pf notes: 1. all timing measurements are defined at the point of signal crossing v dd / 2. 2. these parameters are periodically sampled and are not 100% tested. analog output temperature power supply dc electrical characteristics (cont.) : v dd = +2.7v to +5.5v , v ref h = +v dd , v ref l = 0v, unless otherwise specified symbol parameter conditions min typ max units fso full-scale output voltage v r = v ref h v ref l 0.99 v r 0.995 v r v zso zero-scale output voltage v r = v ref h v ref l 0.005 v r 0.01 v r v i l dac output load current 1 a r out dac output impedance v dd = +5v 100 k ? v dd = +3v 150 k ? pssr power supply rejection i load = 250 na 1 lsb / v tc o v out temperature coefficient v ref h = +5v, v ref l = 0v 200 v/ c v dd = +5v, i load = 250na tc ref temperature coefficient of v ref h to v ref l 700 ppm / c v ref resistance i dd1 supply current (read) normal operating 400 600 a i dd2 supply current (write) v dd =5v 1600 2500 a v dd =3v 1000 1600 a v dd operating voltage range 2.7 5.5 v c l = 100 pf, see note 1
cat524 4 doc. no. 25076-00 rev. 4/01 m-1 a. c. timing diagram t o 1 2 3 4 5 clk cs di do prog t h clk rising clk edge to falling clk edge t l clk falling clk edge to clk rising edge t csh falling clk edge for last data bit (di) to falling cs edge t css rising cs edge to next rising clk edge t csmin falling cs edge to rising cs edge t dis data valid to first rising clk edge after cs = high t dih rising clk edge to end of data valid t do0 rising clk edge to d0 = low t lz rising cs edge to d0 becoming high low impedance (active output) t do1 rising clk edge to d0 = high t hz falling cs edge to d0 becoming high impedance (tri-state) rising prog edge to next rising clk edge falling clk edge after prog=h to rising rdy/ bsy edge t h clk t l clk t csh t css t csmin t dis t dih t do0 t lz t do1 t hz timing from to min/max min min min min min min min max (max) max (max) min min param name rdy/bsy t busy rising prog edge to falling prog edge t ps t prog t prog max t ps t o 1 2 3 4 5 t busy
cat524 5 doc. no. 25076-00 rev. 4/01 pin description pin name function 1v dd power supply positive. 2 clk clock input pin.clock input pin. 3 rdy/ bsy ready/busy output 4 cs chip select 5 di serial data input pin. 6 do serial data output pin. 7 prog eeprom programming enable input 8 gnd power supply ground. 9v ref l minimum dac output voltage. 10 v out 4 dac output channel 4. 11 v out 3 dac output channel 3. 12 v out 2 dac output channel 2. 13 v out 1 dac output channel 1. 14 v ref h maximum dac output voltage. device operation the cat524 is a quad 8-bit digital to analog converter (dac) whose outputs can be programmed to any one of 256 individual voltage steps. once programmed, these output settings are retained in non-volatile eeprom memory and will not be lost when power is removed from the chip. upon power up the dacs return to the settings stored in eeprom memory. each dac can be written to and read from independently without effecting the output voltage during the read or write cycle. each output can also be temporarily adjusted without chang- ing the stored output setting, which is useful for testing new output settings before storing them in memory. digital interface the cat524 employs a standard 3 wire serial control interface consisting of clock (clk), chip select (cs) and data in (di) inputs. for all operations, address and data are shifted in lsb first. in addition, all digital data must be preceded by a logic 1 as a start bit. the dac address and data are clocked into the di pin on the clock s rising edge. when sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. multiple devices may share a common input data line by selectively activating the cs control of the desired ic. data outputs (do) can also share a common line because the do pin is tri-stated and returns to a high impedance when not in use. chip select chip select (cs) enables and disables the cat524 s read and write operations. when cs is high data may be read to or from the chip, and the data output (do) pin is active. data loaded into the dac control registers will remain in effect until cs goes low. bringing cs to a logic low returns all dac outputs to the settings stored in eeprom memory and switches do to its high imped- ance tri-state mode. because cs functions like a reset the cs pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. clock the cat524 s clock controls both data flow in and out of the ic and eeprom memory cell programming. serial data is shifted into the di pin and out of the do pin on the clock s rising edge. while it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to eeprom memory, even though the data being saved may already be resident in the dac control register. no clock is necessary upon system power-up. the cat524 s internal power-on reset circuitry loads data from eeprom to the dacs without using the external clock. as data transfers are edge triggered clean clock transi- tions are necessary to avoid falsely clocking data into the control registers. standard cmos and ttl logic fami- lies work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. dac addressing is as follows: dac output a0 a1 v out 1 0 0 v out 2 1 0 v out 3 0 1 v out 4 1 1
cat524 6 doc. no. 25076-00 rev. 4/01 m-1 complished through the control signals: chip select (cs) and program (prog). with cs high, a start bit followed by a two bit dac address and eight data bits are clocked into the dac control register via the di pin. data enters on the clock s rising edge. the dac output changes to its new setting on the clock cycle following d7, the last data bit. programming is achieved by bringing prog high for a minimum of 3 ms. prog must be brought high some- time after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the d7 bit. two clock cycles after the d7 bit the dac control register will be ready to receive the next set of address and data bits. the clock must be kept running through- out the programming cycle. internal control circuitry takes care of ramping the programming voltage for data transfer to the eeprom cells. the cat524 eeprom memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. reading data each time data is transferred into a dac control register currently held data is shifted out via the d0 pin, thus in every data transaction a read cycle occurs. note, however, that the reading process is destructive. data must be removed from the register in order to be read. figure 2 depicts a read only cycle in which no change occurs in the dac s output. this feature allows ps to poll dacs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in eeprom so that it can be restored at the end of the read cycle. in figure 2 cs returns low before the 13 th clock cycle completes. in doing so the eeprom s setting is reloaded into the dac control register. since v ref v ref , the voltage applied between pins v ref h andv ref l, sets the dac s zero to full scale output range where v ref l = zero and v ref h = full scale. v ref can span the full power supply range or just a fraction of it. in typical applications v ref h andv ref l are connected across the power supply rails. when using less than the full supply voltage v ref h is restricted to voltages between v dd and v dd /2 and v ref l to voltages between gnd and v dd /2. ready /busy /busy /busy /busy /busy when saving data to non-volatile eeprom memory, the ready/busy ouput (rdy/ bsy ) signals the start and duration of the eeprom erase/write cycle. upon receiv- ing a command to store data (prog goes high) rdy/ bsy goes low and remains low until the programming cycle is complete. during this time the cat524 will ignore any data appearing at di and no data will be output on do. rdy/ bsy is internally anded with a low voltage detec- tor circuit monitoring v dd. if v dd is below the minimum value required for eeprom programming, rdy/ bsy will remain high following the program command indicat- ing a failure to record the desired data in non-volatile memory. data output data is output serially by the cat524, lsb first, via the data out (do) pin following the reception of a start bit and two address bits by the data input (di). do becomes active whenever cs goes high and resumes its high impedance tri-state mode when cs returns low. tri-stating the do pin allows several 524s to share a single serial data line and simplifies interfacing multiple 524s to a microprocessor. writing to memory programming the cat524 s eeprom memory is ac- figure 2. reading from memory figure 1. writing to memory a0 a1 1 do di cs prog dac output t 1 2 3 4 5 6 7 8 9 10 11 12 o current dac value non-volatile d0 d1 d2 d3 d4 d5 d6 d7 current dac data d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dac data current dac data current dac value non-volatile dac output prog do di cs new dac value volatile new dac value non-volatile t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o
cat524 7 doc. no. 25076-00 rev. 4/01 application circuits this value is the same as that which had been there previously no change in the dac s output is noticed. had the value held in the control register been different from that stored in eeprom then a change would occur at the read cycle s conclusion. temporarily change output the cat524 allows temporary changes in dac s output to be made without disturbing the settings retained in eeprom memory. this feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. figure 3 shows the control and data signals needed to effect a temporary output change. dac settings may be changed as many times as required and can be made to any of the four dacs in any order or sequence. the temporary setting(s) remain in effect long as cs remains high. when cs returns low all four dacs will return to the output values stored in eeprom memory. when it is desired to save a new setting acquired using figure 3. temporary change in output this feature, the new value must be reloaded into the dac control register prior to programming. this is be- cause the cat524 s internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no prog signal is received. d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 1 new dac data current dac data do di cs prog dac output t 1 2 3 4 5 6 7 8 9 10 11 12 n n+1 n+2 o current dac value non-volatile new dac value volatile current dac value non-volatile bipolar dpp output msb lsb 1111 1111 (.98 v ) + .01 v = .990 v v = +4.90v 1000 0000 (.98 v ) + .01 v = .502 v v = +0.02v 0111 1111 (.98 v ) + .01 v = .498 v v = -0.02v 0000 0001 (.98 v ) + .01 v = .014 v v = -4.86v 0000 0000 (.98 v ) + .01 v = .010 v v = -4.90v ref ref ref if v = 5v ref 255 255 out dac input dac output analog r = r output ref ref ref out 128 255 127 255 ref ref ref out 1 255 ref ref ref out ref ref ref out 0 255 v = 0.99 v fs ref v = 0.01 v zero ref v = (v - v ) + v dac code 255 fs zero zero amplified dpp output opt 504 gnd v dd v h ref v l ref control & data + op 07 v out -15v +15v +5v rr i f v = (1 + ) v out dac r f r i cat524 cat524 gnd v dd v h ref v l ref control & data + op 07 ( ) -v r f r + i -15v +15v +5v rr i f r i i r f v dac for r = i r f v = 2v -v out i dac v i v out out v =
cat524 8 doc. no. 25076-00 rev. 4/01 m-1 application circuits (cont.) coarse-fine offset control by averaging dpp outputs for single power supply systems coarse-fine offset control by averaging dpp outputs for dual power supply systems digitally trimmed voltage reference digitally controlled voltage reference opt 505 lt 1029 i > 2 ma v+ gnd v dd v = 5.000v ref v h ref v l ref control & data cat514 gnd v dd v h ref v l ref control & data + 15k 10 f 5.1v 10k 4.02 k 1.00k 10 f 35v lm 324 1n5231b mpt3055el 28 - 32v output 0 - 25v @ 1a cat524 cat524 + fine adjust dpp coarse adjust dpp gnd v l ref v h ref v dd r c 127r c +v +5v v ref r = c 256 1 a v ref * fine adjust gives 1 lsb change in v when v = offset v ref 2 offset v offset + fine adjust dpp coarse adjust dpp gnd v l ref v h ref v dd r c 127r c +v +5v +v ref -v -v ref r o r = c 1 a offset v offset ref (+v ) - (v ) r = o 1 a offset ref (-v ) + (v ) + +
cat524 9 doc. no. 25076-00 rev. 4/01 application circuits (cont.) staircase window comparator overlapping window comparator cat524 + + + + + + + + 10k +5v window 2 10k +5v window 3 10k +5v window 4 10k +5v window 5 + + 10k +5v window 1 gnd v l ref cs di do prog clk v dd v h ref v ref +5v 1.0 f lm 339 dpp 1 dpp 2 dpp 3 dpp 4 window 1 window 2 window 3 window 4 window 5 v ref v 1 out v 2 out v 3 out v 4 out gnd window structure v in cat524 + + + + + + + + 10k +5v window 2 10k +5v window 3 10k +5v window 4 10k +5v window 5 + + 10k +5v window 1 gnd v l ref cs di do prog clk v dd v h ref v ref +5v 1.0 f lm 339 dpp 1 dpp 2 dpp 3 dpp 4 window 1 window 2 window 3 window 4 window 5 v ref v 1 out v 2 out v 3 out v 4 out gnd window structure v in
cat524 10 doc. no. 25076-00 rev. 4/01 m-1 application circuits (cont.) current sink with 4 decades of resolution current source with 4 decades of resolution gnd v l ref v dd v ref +5v dpp + cat524 control & data dpp + 10k 10k 39 ? 1w lm385-2.5 5 a steps i = 2 - 255 ma sink 2n7000 10k 10k tip 30 39 ? 1w 5m 3.9k + -15v 2n7000 +5v +15v 4.7 a 1 ma steps 2.2k h 5m gnd v l ref v dd v h ref +5v dpp + cat524 control & data dpp + 5m 5m 39 1w 39 1w 5m 5m 3.9k lm385-2.5 -15v 5 a steps i = 2 - 255 ma source 1 ma steps + 10k 10k +15v tip 29 bs170p bs170p 51k ? ?
cat524 11 doc. no. 25076-00 rev. 4/01 application circuits (cont.) v pp cs prog di do clk v dd v h ref v l ref v 3 out v 2 out v 1 out v 4 out gnd 14 1 13 12 11 10 9 8 4 7 5 6 2 3 47k 47k 47k 47k 1.0 f 0.22 f 0.22 f 0.22 f 0.22 f 14 11 5 16 9 23 3 22 1 7 18 17 21 24 12 out 2 15 out 1 10 13 4 8 +12v v cc treb cap bass cap output 1 bypass output 2 treb cap bass cap gnd gnd stereo enhance in 2 volume balance treble bass loudness v in 1 z 19 2 lm1040 opt 504 chip select. program data in data out clock input 2 20v in5250b 2.5 f input 1 1.0 f 1n914 1n914 +12v .005 f 10k 74c14 0.47 f 0.47 f 0.1 f 4.7k 0.1 f 0.01 f 0.39 f 47 f 10 f 10 f 0.39 f 0.01 f digital stereo control cat524
cat524 12 doc. no. 25076-00 rev. 4/01 m-1 ordering information notes: (1) the device used in the above example is a cat524ji-te13 (soic, industrial temperature, tape & reel) prefix device # suffix 524 j product number package p: pdip j: soic cat optional company id i temperature range blank = commercial (0 ? c to +70 ? c) i = industrial (-40 ? c to +85 ? c) -te13 tape & reel te13: 2000/reel

▲Up To Search▲

Price & Availability of CAT524P-TE13

	To Download CAT524P-TE13 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .